The invention relates to the field of electrical circuit design, and more particularly, to the field of timing model extraction.
Timing extraction or block characterization refers to the process of creating a timing model of a digital circuit for use with a timing analyzer, e.g., a static timing analyzer. Timing extraction plays an important role in hierarchical top-down flow and bottom-up IP authoring flow by reducing the complexity of timing verification and by providing a level of abstraction which hides the implementation details of IP blocks. Three desired features in timing extraction are accuracy, efficiency, and usability.
The extracted model should preserve the timing behavior of the original circuit and produce accurate results including correct transparent latch behaviors and timing violations. The model also needs to be efficient in terms of the resources needed to generate the model and in terms of the final model size. The model should also be easy to use with existing static timing analyzers. This includes model instantiation, translation of original timing constraints and easy-to-follow timing reports.
Timing model can often be classified into two types: black box model and gray box model. Black box models have no internal visibility into the block—all the timing information relates to the pins at the boundary of the block. Gray box models, on the other hand, have internal pins that allow for modeling behaviors like time borrowing across multiple latches. Such internal pins provide advantages such as capability to reduce model size and capability to apply original timing constraints or assertions.
In one approach for implementing a black box model, users supply a set of input slew values and output load values and the tool performs path tracing to determine all port-to-port path delays and relevant timing checks. Although black box models have been widely used, they suffer from significant drawbacks. For example, tracing each possible path in the timing graph is a potentially complex task that could consume a significant amount of computing resources—often requiring a full timing analysis process to extract a model. Moreover, the resulting model size in this approach may actually end up larger than the original timing graph size. This is illustrated in FIG. 1, in which path tracing is employed to derive a black box model 140 from a timing graph 100. In this approach, every potential path is identified by tracing from an individual input port to an individual output port. Thus, the path through arc 102 and arc 108 in the original timing graph 100 is traced through pin 150 to form path 120 in the black box model 140. Tracing each possible path results in nine arcs or paths in the resulting timing model 140 (arcs 120, 122, 124, 126, 128, 130, 132, 134, and 136). As can be seen, there are only six arcs in the original timing graph 100 (arcs 102, 104, 106, 108, 110, and 112). Thus, the black box model 140 is actually larger than the original timing graph 100.
Another drawback with known black box models is that only limited latch behavior can be modeled. The model can capture the latch time borrowing behavior of the original netlist for some given clock waveforms. If the clock waveforms change after the model is extracted, the model becomes invalid. Moreover, support for assertions in black box models is limited, even for those assertions that are fully contained in the block. Only assertions that originate from and terminate at boundary ports can be fully supported. For example, multi cycle paths that do not originate from or terminate at boundary ports cannot be supported. Also, assertions that span multiple blocks cannot be supported. For example, consider a multi cycle path that originates from block A and terminates in the middle of block B. The black box model for block B cannot support this multi cycle path assertion.
Approaches to gray box modeling also suffer from drawbacks. Conventional gray box approaches cannot adequately handle arbitrary levels of transparency in latches. Latches may be transformed to registers or combinational gates but such transformations could lead to models that are too conservative and do not allow for time borrowing. One approach provides latch path compression work that collapses latch paths instead of individual latches, in which the extent of compression is controlled by specifying the desired level of latch transparency. However, this approach cannot guarantee a reduction in model size and in some cases, the model size actually increases after latch path compression. Moreover, the method does not scale well with the number of latch paths or with the level of latch transparency.